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CoProVision: Automatic Co-Processor Generation for Vision Applications

CoProVision shall be a joint collaborative project between Vision Image & Signal Processing (VISpro) Lab at SEECS-NUST and Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany. The project aims to propose schemes for automatic generation of high-performance hardware accelerators and coprocessors specially targeted for the domain of Digital Image Processing and Computer Vision. This shall enable generation of performance-efficient hardware accelerators that can be reconfigured on FPGAs to expedite different image processing and computer vision applications such as stereo reconstruction, object tracking, video registration and geometrical warping. As an example a co-processor speeding-up “Feature Matching” can be instantiated in an application specific processor performing stereo reconstruction to accelerate the overall design

Project Modules
Two sub projects shall be carried out initially under this title:
  • An Automatic Coprocessor Generation Methodology for Computer Vision based Applications
    This project shall aim at devising an automatic co-processor generation methodology specially tailored for Computer Vision applications. An updated literature survey (Papers to be selected from/related to the  References identified in Section-6) shall be carried out comparing the state of the art schemes for automatic instruction identification and selections. A minimum of three such schemes shall be implemented and their performance reported for a few basic image and vision based applications. Strength and weakness of selected schemes shall be reported and a new scheme improving upon their deficiency shall be proposed. 
  • Design Space Exploration of Automatically-Generated Hardware Accelerators for Various Feature Matching Algorithms
    Feature matching is an important step in many Computer Vision applications such as 3D reconstruction, multi view imaging and video registration. Furthermore, regardless of the particular Feature Extraction scheme chosen any feature matching scheme can be typically employed to match the relevant features and discard others. Thus an efficient co-processor for feature matching can thus enhance the performance of a number of vision applications. This project shall aim at performing a comparison of popular Feature matching algorithms; selection of the best scheme based upon its suitability for implementation on hardware (FPGA) and finally performing design space exploration using existing ‘automatic’ hardware acceleration schemes. 
Team at CES KIT
Team at NUST
  • Dr. Rehan Hafiz
  • Rana M Bilal (PG Research)
  • Saad Shoaib (PG Research)
  • Amir Asim Khan (PG RA)
  • Arbab Latif (PG RA)
 Rana Muhammad Bilal, Rehan Hafiz, Muhammad Shafique, Saad Shoaib, Asim Munawar, Jörg Henkel, ISOMER: Integrated Selection, Partitioning and Placement Methodology for Reconfigurable Architectures, IEEE/ACM 31st, International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 2013, (accepted).