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Project Coordinator - UHD Panorama Generation System

posted 11 Nov 2014, 06:47 by Rehan Hafiz

Vision Imaging & Signal Processing (VISpro) Lab at SEECS-NUST is looking for Project Coordinator for one of  its collaboration project. The project is in collaboration with Electrical & Telecommunication Research Institute (ETRI) to develop an Ultra High Definition (UHD) Panorama generation system. The system is aimed at producing immersive larger-then-life visual contents from multiple independent camera arrays and finally projecting them seamlessly on multiple projectors.

Minimum Required Skill Set:
- Word, PhP, Excel
- Programming Experience in OpenCv, MATLAB & C/C++
- Experience in project related to Image Processing / Computer Vision
- GPA above 3.0 ( Less GPA is acceptable only if have Conference Publication or any Programming 

- Candidate must be holding a UG Degree

Please send your CV via email to Lab Director

Paper accepted in ICCAD 2013

posted 13 Aug 2013, 05:59 by Rehan Hafiz

A collaborative effort between Vispro LAb & Chair for Embedded Systems (http://ces.itec.kit.edu/)  resulted in a paper being accepted at the ICCAD 2013 Conference. For more details related tot he project please click here : https://sites.google.com/site/visprogroup/home/coprovision

R&D Positions @ VISpro LAB SEECS - NUST for an International Collaboration Project

posted 16 May 2013, 04:51 by Rehan Hafiz

Google Spreadsheet Form

R&D Position @ VISpro LAB SEECS - NUST

posted 16 May 2013, 04:47 by Rehan Hafiz   [ updated 16 May 2013, 04:49 ]

Google Spreadsheet Form

Talk by Dr. Muhammad Shafique from KIT Germany on 17th & 18th of Jan 2013

posted 16 Dec 2012, 11:36 by Rehan Hafiz   [ updated 16 Dec 2012, 11:37 ]

Dr. Muhammad Shafique from Chair of Embedded Systems (KIT Germany) and VISpro Lab (SEECS) are collaborating on the area of Automatic Co-Processor Generation for Computer Vision (Co-Pro-Vision). Dr. Shafique shall be giving two talks on 17th & 18th of January 2013(1700 hrs @ SEECS Seminar Hall).  An abstract of the two talks and an introduction to the presenter is provided below.

Title: Cross-Layer Techniques for Reliable Code Generation and Execution on Unreliable Hardware

Venue & Time: SEECS Seminar Hall @ 1700 hrs on 17th of January 2013

Abstract: In the deep nano-scale regime, reliability has emerged as one of the major design constraints for high-density integrated systems. Among others, key reliability-related issues are soft errors, temperature related issues, and aging effects like Negative Bias Temperature Instability, which may corrupt the correct execution of application software. Tremendous amount of research effort has been invested at device, circuit, and architecture levels to counter these problems. However, these techniques incur significant area and power cost. We believe that designing a highly reliable and robust system requires combating the reliability issues at all the system layers, i.e. ranging from device to all the way up to the application software. In particular, we propose various reliability-optimizing techniques at compilation, system software, and application levels that account for the hardware’s susceptibility to various types of errors. Our proposed techniques enable generation and execution of reliable application software code, which minimizes the error probability on potentially unreliable hardware. This talk provides an overview of important reliability issues and state-of-the-art techniques along with several compilations and system software techniques for reliable systems and resiliency modeling approaches currently under investigation in our lab.

Title: Developing Power-Efficient Embedded Multimedia Systems for 3D-Video Coding

Venue & Time: SEECS Seminar Hall @ 1700 hrs on 18th of January 2013

Abstract: Due to the recent advancements in display and camera technologies, new 3D-video services are emerging that will change the landscape of future entertainment, security, and communication industries. Prominent application scenarios are Free Viewpoint TV, Realistic-TV, 3D-personal video recording and playback, 3D-surveillance, in-car 3D-infotainment, etc. However, gigantic amount of data processing poses a grand challenge towards next-generation embedded multimedia computing. We believe that exploiting the extensive application specific knowledge and leveraging algorithm- architecture collaborative techniques is the key to achieve high energy efficiency. This talk will provide an overview of performance and power related challenges for designing emerging embedded multimedia systems for 3D-video coding. Various energy-efficient algorithm and architecture level techniques will be presented that enable low-power processing of 3D-video coding.

About the Presenter

Dr. Muhammad Shafique is a research group leader at the Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He has 9+ years' research and development experience in low-power and high-performance embedded systems (covering both hardware & software perspectives) in leading industrial and research organizations. Dr. Shafique holds one US patent on the low cost operational control for video encoders, 6 Gold Medals, CODES+ISSS'11 Best Paper Award, AHS'11 Best Paper Award, DATE'08 Best Paper Award, ICCAD'10 Best Paper Nomination, seven HiPEAC (European Network of Excellence on High Performance and Embedded Architecture and Compilation) Paper Awards, and Best Master's Thesis Award. He has (co) -authored 1 book and 45+ publications in premier conferences and journals on various aspects of low- power, reliable, and adaptive embedded systems.

Information Seminar : MVI Hardware Implementation Design

posted 5 Dec 2012, 22:24 by Rehan Hafiz   [ updated 5 Dec 2012, 22:26 ]

Registration Form : Information Seminar : A Multi View Imaging ‎‎‎(MVI)‎‎‎ Processing Platform: Real Time Panoramic Mosaic Generation


RA Position @ UHD Project

posted 24 May 2012, 00:04 by Rehan Hafiz

If you have strong problem solving skills, love developing algortihms & have a desire to initiate your career in cutting edge research & development --- here is an oppurtunity. Vision Imaging & Signal Processing (VISpro) Lab at SEECS-NUST is looking for a Research Assistant with strong analytical & algorithmic background. The project is in collaboration with Electrical & Telecommunication Research Institute (ETRI) to develop an Ultra High Definition (UHD) Panorama generation system. The system is aimed at producing immersive larger-then-life visual contents from multiple independent camera array. Minimum Required Skill Set: - Programming Experience in MATLAB/C/C++ - Experience in project related to Image Processing / Computer Vision - GPA above 3.25 ( Less GPA is acceptable only if have Conference Publication or any Programming Honour) Plus Points if : - You have published a paper/s - Experience with OpenCV Eligibility: - Computer Science with emphasis in Computer Vision, Computer Engineering & EE Graduates with proven experience in Computer Vision are encouraged to apply About Job: - Full Time Position - Students who wish to do MS @ SEECS-NUST with RAShip can also apply Last Date to Apply: - 25th May 2012

VISpro Summer Internships

posted 31 May 2011, 02:10 by Rehan Hafiz   [ updated 31 May 2011, 02:30 ]

VISPro Summer 2011 Internships ‎‎‎(Multiple Projects 3000-5000 Rs./Month)‎‎‎

Exciting RA/Developer Positions @ VISpro LAB

posted 24 Feb 2011, 22:37 by Rehan Hafiz   [ updated 31 May 2011, 02:50 ]

Two new RA/Developer positions are open @ VISpro Lab currently.

For Further details & to apply for job please click the relevant post:
  • These Positions are now closed
Last Date to Apply : 2nd March 2011

Numetrics collaborates with VISpro-SEECS to upgrade Complexity Calculation for NMX Schedule Risk Analyzer™

posted 21 Feb 2011, 01:03 by Rehan Hafiz

Numetrics has recently initiated a research study at VISPRO-SEECS. It aims at next level classification of generic hardware functional modules, for up gradation of its complexity calculation engine of NMX Schedule Risk Analyzer™. This classification is to be derived with input from latest research in this area and from renowned individuals of chip design process in academia and industry. The work is being carried out by Rana M Bilal an MS student of MS-DSP-EE-2 at SEECS.

About Numetrics

Numetrics provides semiconductor and embedded systems companies with fact-based product- development planning software that lays the foundation for improved productivity. Numetrics enterprise resource planning (ERP) software gives managers the power to calculate their project’s development complexity and schedule risk and to benchmark their team against the competition. Armed with that unmatched insight, managers can staff projects to more efficient levels, eliminate schedule slip and turn product development from a cost center into a profit center.

For Further Information : http://www.numetrics.com/

About NMX Schedule Risk Analyzer™

The NMX Schedule Risk Analyzer™ is a product from Numetrics that quantitatively determines the likelihood that an IC project’s development schedule can be achieved. Risk Analyzer operates by calculating not only the development productivity implied in the project plan, but also the implied development throughput. It calculates the development throughput that the project team must achieve to meet its target schedule.

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